Memory entities — Ram, Rom, FtAhbRam¶
Memory is modelled by generic, arch-agnostic entity-peripherals: the entity owns the storage and the bus mounts it as a direct fast region. There is no engine-owned RAM special case — the primary RAM, the boot PROM, and any extra on-chip block (e.g. the GR712RC FTAHBRAM) are all instances of the same two classes.
Ram¶
tero::peripherals::Ram (tero/peripherals/ram.hpp) — a zero-initialized
volatile block. Three capabilities:
| Capability | Consumer | Behaviour |
|---|---|---|
bus::IRamBacking |
Soc assembly | The bus mounts the storage with SystemBus::map_ram_backing — reads, writes and fetches take the same zero-virtual-call fast path as before the entity refactor. |
IMemoryRegion |
debugger / loaders | Span-based bulk read_at/write_at. |
IMmio |
add_peripheral / direct mapping |
Typed word/half/byte fallback when the entity is mapped as a plain peripheral. |
Wait states are deliberately not modelled (timing is the global
EmulatorConfig::cpi, not per-device).
In a machine script:
The first mapped Ram is the primary: compose lowers it to
ram_base/ram_size (validation, initial %sp, loader bounds) and the
engine creates its entity (ram0). Every additional Ram lowers to an entity
spec of its own.
Rom¶
tero::peripherals::Rom — a Ram whose content is fixed at construction
(fill byte + optional image prefix) and that rejects every write path. It is
mounted read-only: the bus itself fails CPU, typed, atomic and DMA writes
with BusError (a SPARC data-access trap) before the entity is consulted —
a write to ROM is a guest bug worth surfacing, not a silent drop. Read-only
backings never enter the u32 fast cache or the JIT's ram_view_at window.
The boot PROM is a Rom instance (prom0) parameterised by cfg.prom_*;
the mkprom2 ELF flattening stays in the runtime loader — loader policy, not
storage behaviour.
FtAhbRam (GR712RC)¶
The GR712RC on-chip memory with EDAC (GR712RC-UM §6) is composed of two generic pieces in the kit:
new Ram name=ftahbram_mem
map memspace=mem0 addr=0xA0000000 size=192K object=ftahbram_mem
new FtAhbRam name=ftahbram0
map memspace=mem0 addr=APB2 size=REG object=ftahbram0
tero::peripherals::FtAhbRam models only the APB configuration register at
0x80100000 (Table 36):
| Bits | Field | Behaviour |
|---|---|---|
| 31:30 | DIAG | RAM timing adjust — not modelled; writes ignored, reads 0 |
| 23:21 | MEMSIZE (MSB) | read-only, hardcoded 001 |
| 20:13 | SEC | single-error counter, W1C per bit — always 0 (fault-tolerance Level 2: the memory never degrades) |
| 12:10 | MEMSIZE (LSB) | read-only, hardcoded 000 |
| 9 / 8 / 7 | WB / RB / EN | stored read/write; EDAC check-bit flow is not modelled at Level 2 |
| 6:0 | TCB | test check bits, stored read/write |
Word-only access (non-word → AlignmentError). No IRQ. Not published in the
PnP tables — the GR712RC carries it in the historic device set without a PnP
record.