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MemCtrl (FTMCTRL) — Memory controller stub

GRLIB FTMCTRL (GR712RC §5 / GRLIB IP §17): the fault-tolerant memory controller with EDAC. In Lince this is a passive stub — enough to satisfy RTEMS BSP probes, with no timing, bank switching, or EDAC behaviour.

Property Value
Default MMIO base 0x80000000
MMIO window size 0x100
IRQ —
Source file src/peripherals/src/memctrl.cpp

Register map

All registers are 32-bit, word-aligned, word-only. Byte and half-word accesses return ErrorCode::AlignmentError.

Offset Name Access Reset value Description
0x00 MCFG1 R/W 0x00000F00 PROM configuration (wait states, width)
0x04 MCFG2 R/W 0x00000000 SRAM / SDRAM configuration
0x08 MCFG3 R/W 0x08000000 EDAC / refresh control
0x0C MCFG4 R/W 0x00000000 RS-EDAC diagnostics

Accesses outside 0x00–0x0C return BusError.

Behaviour

The stub treats the four registers as opaque storage:

  • Writes store the value as-is.
  • Reads return the last written value.
  • tick() is a no-op; there are no timed side effects.
  • IRQ / DMA: None.

The only bit-level exception is MCFG3 bit 27:

Bit Name Behaviour
27 Reserved (hardware tie-off) Read: always returns 1 regardless of the stored value. Write: masked to 0 on store, so software can never clear it.

This matches the GR712RC hardware where MCFG3 bit 27 is a reserved bit that reads as 1.

Reset state

Register Reset value
MCFG1 0x00000F00
MCFG2 0x00000000
MCFG3 0x08000000
MCFG4 0x00000000

AMBA Plug & Play

MemCtrl itself does not implement PnP registers. However, the emulator runtime fabricates an AHB Slave Plug & Play descriptor during Emulator::initialize() so that RTEMS auto-probing works:

  • Vendor ID: 0x01 (Gaisler)
  • Device ID: 0x054 (FTMCTRL)
  • PnP config word: 0x01054020 (at 0xFFFFF820)
  • Address descriptor: 0x4000fff1 (at 0xFFFFF830)

This was corrected from the initial placeholder 0x00F (plain MCTRL) during the 2026-04-24 hardware audit (Decision 33).

Why a stub?

Full SDRAM timing, bank switching, refresh scheduling, and EDAC scrubbing are out of MVP scope. RTEMS only needs to read the configuration registers during early boot to determine memory width and presence; after that it never touches the FTMCTRL again. The stub is sufficient for the entire RTEMS testsuite.

Tests

  • tests/unit/test_memctrl.cpp — 6 test cases covering reset values, read/write round-trips, the MCFG3 bit-27 tie-off, non-word access rejection, out-of-range offsets, and reset-after-write.
  • Integration tests exercise the stub implicitly through the RTEMS boot path.