Tero¶

A C++20 functional emulator for the LEON3 / LEON4 SPARC V8 processors, designed to boot the RTEMS testsuite and to be wrapped as an SMP2 simulation model for the European space industry.

Tero emulates the GR712RC (dual-core LEON3FT) and GR740 (quad-core LEON4FT) System-on-Chips at the functional level: the CPU, memory, bus, interrupt controller, timers, UART and FPU are modelled with bit-accurate register semantics. SRMMU and cache control are deliberately deferred — see the roadmap for the rationale.

Choose your manual¶

What is this hardware?¶

If you are new to the LEON/GRLIB ecosystem, here is the one-paragraph context:

Cobham Gaisler (part of Frontgrade) designs radiation-hardened 32-bit processors for space applications. The LEON3 and LEON4 cores implement the SPARC V8 instruction set — a classic, well-specified RISC ISA. The GR712RC (dual-core LEON3FT) and GR740 (quad-core LEON4FT) are SoC families used in real satellites and launchers across the European space industry. They run RTEMS — the Real-Time Executive for Multiprocessor Systems, the standard open-source RTOS for safety-critical embedded applications. Developing software for these targets normally requires either physical hardware (expensive, shared, often flight-locked) or Gaisler's own SIS simulator (closed-source, limited scripting). Tero fills that gap: an open-source, embeddable, RTEMS-validated functional emulator for the same silicon.

Where Tero fits¶

Tero targets a specific point in the LEON-simulator space: functional accuracy at the register level, open-source, embeddable as a C++ library, and architected for SMP2 wrapping. The reference oracle for correctness is Gaisler's SIS simulator — Tero matches it instruction- and register-by-register where they can be compared.

It boots RTEMS to completion across uniprocessor (N=1), GR712RC SMP (N=2) and GR740 SMP (N=4) configurations, under both the Switch interpreter and the LLVM JIT, and supports custom peripherals via a single-file IPeripheral implementation. See Testing for current pass rates and the known-failures breakdown.

Capabilities¶

Quick example¶

#include "tero/runtime/emulator.hpp"
#include "tero/runtime/emulator_config.hpp"

int main() {
    auto cfg = tero::compose::gr712rc_config();
    cfg.num_cores = 2;
    cfg.ram_size  = 16 * 1024 * 1024;

    auto emu = tero::runtime::Emulator::create(cfg).value();
    emu->initialize();
    emu->load_elf("rtems_hello.elf");

    auto result = emu->run_for(tero::SimTimeNs{5'000'000'000ULL});
    // UART output already written via the injected ICharacterDevice.
}

Or from the shell:

./build/src/app/tero-emu --image rtems_hello.elf --cores 2 --budget 5000000000

Get started in 5 minutes Read the architecture

Project status¶

The MVP (Phases 0–6) and most follow-up scope (FPU, GDB stub, SMP validation, Save/Restore, PROM) are complete, plus the Phase 9–15 work toward 1:1 real-time GR740 (arch-neutral IR, tiered LLVM JIT, MultiThread execution). The full CTest suite passes, RTEMS hello-world boots cleanly through the APBUART, sptests / fptests / smptests are exercised in CI, and the GDB stub speaks RTEMS-aware thread queries against live guests.

Roadmap Detailed status

SMP2 readiness¶

The architecture follows the ECSS-E-ST-40-07 lifecycle:

Publish() → Configure() → Connect() → Initialize() → Run() → Hold() → Store() → Restore()

…even though the SMP2 wrapper itself is not part of the MVP. Every external service the core needs is injected through an interface, so the wrapper is an adapter layer rather than a refactor of the core.

SMP2 design notes

License¶

Tero source code is released under the Apache License 2.0. Vendored third-party components retain their upstream licenses (see THIRD_PARTY_LICENSES.txt).