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Roadmap

Current state: Phases 0–6 are complete. 263 tests pass, RTEMS hello-world boots cleanly, and 10 RTEMS sptests reach *** END OF TEST.

Phase 7 is the "Run real RTEMS workloads" milestone. Phase 8 is the "System-level simulation" milestone.

Phase 7 — FPU, MMU, GDB, SMP, cache

Mission: maximise RTEMS testsuite coverage and enable interactive debugging of real guests.

Phase 7 exit criteria

  • ≥ 80 % of RTEMS 5 sptests pass (uniprocessor, no MMU).
  • ≥ 50 % of RTEMS 5 smptests pass (N=2 GR712RC, N=4 GR740).
  • 100 % of fptests that do not require extended fenv pass.
  • RTEMS 5 hello-world boots and completes cleanly with MMU enabled.
  • A remote GDB session works against an RTEMS binary (breakpoints, single-step, register and memory inspection).

7.1 Advanced FPU (Berkeley SoftFloat 3e)
Goal Replace the FPU stub with a faithful IEEE-754 SPARC V8 FPU. Unblocks dozens of sptests that currently fail on FP-disabled traps.
Status In progress — Tanda 1 core operations implemented; TEM-gated fp_exception trap and RTEMS fptest01 integration pending.
Key deliverables fpu.hpp, fpu_handlers.hpp, softfloat_context.hpp and matching .cpp files in src/core/. Vendored third-party/softfloat3e/.
Dependencies Phase 3 trap dispatch (done).

7.2 SRMMU (SPARC V8 Reference MMU)
Goal Enable the RTEMS-with-MMU testsuite (process isolation, paging). Scope is RTEMS, not Linux.
Status Pending
Key deliverables mmu.hpp, mmu_pte.hpp, mmu.cpp, mmu_walker.cpp; ASI 0x4 register file; ASI 0x3 flush/probe; optional software TLB.
Dependencies Trap system (done); 7.5 Cache Control Registers (prerequisite, shares the alternate-space dispatch path).

7.3 GDB remote stub
Goal Enable interactive debugging of the guest via the GDB Remote Serial Protocol over TCP.
Status Done — RSP over TCP, 9 GDB tests pass; conditional E2E with sparc-rtems5-gdb skips cleanly when absent.
Key deliverables gdb_stub.hpp / gdb_stub.cpp in src/runtime/. Software breakpoints, multi-core thread exposure, vCont, Ctrl-C interrupt.
Dependencies None. Recommended before 7.2 because debugging page-table failures without a debugger is unnecessarily difficult.

7.4 SMP validation (GR712RC N=2, GR740 N=4)
Goal Validate the SMP-ready architecture by booting RTEMS smptests on dual-core and quad-core recipes.
Status Pending
Key deliverables gr740_config() factory; parameterised IrqMP for 1–4 CPUs; GR740 peripheral addresses; tests/integration/test_rtems_smptests.cpp.
Dependencies 7.1 (FPU) and 7.2 (MMU) are desirable first, because several smptests use floating-point and/or MMU.

7.5 Cache control registers (formal stubs)
Goal Replace ad-hoc cache-register patches with a formal, testable model of ASI 0x02. Caches are always disabled but frozen-coherent; writes are logged no-ops.
Status Pending
Key deliverables cache_control.hpp / .cpp in src/core/; CCR writable-bit masking; FI/FD self-clearing flush hints; ICS/DCS always read back 00.
Dependencies None. Recommended immediately before 7.2 (MMU). 
7.1 FPU (finish TEM gating + fptest01)
   ↓
7.3 GDB (already done)
   ↓
7.5 Cache control (small, unblocks MMU)
   ↓
7.2 SRMMU (most complex; tackle with GDB available)
   ↓
7.4 SMP validation (needs FPU + MMU)

Phase 8 — System-level simulation

Mission: enable integration into European space industry simulation environments and turn Lince into a production simulation model.

Step Title Goal Status
8.1 Save / Restore lifecycle Bit-exact Store() / Restore() for SMP2 compliance and checkpointing. Pending
8.2 PROM (boot ROM) Immutable boot ROM at 0x00000000 for real boot flows (MKPROM2). Pending
8.3 Flash memory Programmable non-volatile storage with optional host-file persistence. Pending
8.4 GPIO (GRGPIO) Pin-level connectivity with external models (sensors, actuators). Pending
8.5 CAN bus (HurriCANe / OCAN) Standard space-platform service bus with Rx/Tx mailboxes. Pending
8.6 SpaceWire (GRSPW2) High-speed DMA-based inter-model connectivity with RMAP support. Pending
8.7 RegisterBank pattern Internal refactor: replace bespoke switch-block MMIO with a declarative helper. Pending

Phase 8 exit criteria

  • Store() → modify guest → Restore() reproduces bit-exact state.
  • Cross-model demo: two Emulator instances communicate over SpaceWire RMAP.
  • INTEGRATION.md document describes how to wrap Lince in an SMP2 wrapper.

Dependency graph

Phase 6 (Done)
    |
    +---> 7.1 FPU ----------------------+
    |       (In progress)                |
    +---> 7.3 GDB Stub (Done) ---------+
    |                                   |
    +---> 7.5 Cache Control (Pending) --+---> 7.2 SRMMU (Pending) --+
                                        |                            |
                                        +----------------------------+---> 7.4 SMP (Pending)

Phase 8 items land after Phase 7:
    8.1 Save/Restore -> 8.2 PROM -> 8.3 Flash -> 8.4 GPIO -> 8.5 CAN -> 8.6 SpaceWire
    8.7 RegisterBank is a background refactor (last priority).

Notes

  • The master plan lives in plans/phase7-roadmap.md and its sub-plan files (phase7-fpu.md, phase7-mmu.md, phase7-gdb-stub.md, phase7-smp.md, phase7-cache-control.md).
  • The FPU plan (phase7-fpu.md) still lists Tasks 1.10–1.12 as pending even though the master roadmap marks 7.1 broadly complete. The public status reflects the most conservative view: Tanda 1 core is done, TEM trap gating and RTEMS integration remain.