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Roadmap

Current state: the original MVP (Phases 0–6) and most of the follow-up scope (FPU, GDB stub, SMP validation, Save/Restore, PROM) are complete. Tero now boots RTEMS 5 on leon3, passes the SMP gate for both N=2 and N=4 recipes, and exposes a development-grade GDB backend. The performance track has also landed: binary translation (arch-neutral IR + tiered LLVM JIT) is the default execution method, with the Switch interpreter retained as the correctness oracle; LLVM (≥ 18) is now a mandatory build dependency. SRMMU and cache control are deliberately deferred — see notes below.

The authoritative work-tracking document is plans/roadmap.md. This file is its user-facing summary.

Status snapshot

Area Status Notes
MVP (Phases 0–6) Done Core ISA, traps, peripherals, ELF loader, RTEMS hello-world, sptests/fptests/smptests integration tests.
FPU (Berkeley SoftFloat 3e) Done Vendored as third-party/softfloat3e/. Integrated with TEM-gated fp_exception trap. Used by test_rtems_fptests.
GDB remote stub Done RSP over TCP, late-binding attach, qSymbol handshake, RTEMS thread-awareness (executing thread per core), stop-on-ErrorMode with TT → signal mapping. Full reference: Debugging with GDB.
SMP validation (GR712RC N=2, GR740 N=4) Done Above the ≥ 50 % gate: N=2 at 77.8 % (42/54 smptests), N=4 at 74.1 % (40/54).
Save / Restore lifecycle Done SMP2-aligned Store() / Restore() with bit-exact round-trip.
PROM (Boot ROM) Done Immutable boot ROM at 0x00000000; mkprom2 .rom images detected and flattened automatically.
Realtime pacing Done PacingMode::Realtime (default) vs Turbo. CLI --turbo.
Decode cache (Phase 10.1) Done Per-PC direct-mapped decode cache on the Switch path.
Threaded-code dispatch (Phase 10.2) Removed Prototyped to ~1.5× over Switch, missed its exit targets, superseded by the IR JIT. See Design decisions (Decision 59).
Arch-neutral IR (Phase 11) Done Guest-ISA-neutral IrBlock/GuestState; SPARC frontend; IR interpreter. The multi-arch seam.
Tiered LLVM JIT (Phase 12) Done Binary translation is the default (translation = true); baseline O0 + background O2, self-loop/region chaining, inline RAM. ~2000 MIPS on cpubound-mix. LLVM ≥ 18 mandatory. See IR and LLVM JIT.
Cache control registers Deferred Was the prerequisite for SRMMU only; deferred alongside it. Caches remain unmodeled per the original "out of scope" decision.
SRMMU (SPARC V8 MMU) Deferred RTEMS 5 leon3 BSP has no MMU init code and no BSP_USE_MMU flag, so the original primary-goal acceptance ("≥ 50 % MMU sub-suite") is unattainable: that sub-suite does not exist in this RTEMS version. Parked until RTEMS 6 with MMU lands in-tree, or a concrete MMU-using guest appears. See plans/phase7-mmu.md.

Active work — Phase 8 (system-level simulation)

These items extend Tero toward a production simulation model wrappable as an SMP2 (ECSS-E-ST-40-07) component. They are ordered by priority; each lands as an independent feature branch.

Step Title Goal Status
P6 GPIO (GRGPIO) Pin-level connectivity with external models (sensors, actuators). Pending
P7 Flash memory Programmable non-volatile storage with optional host-file persistence. Pending
P8 CAN bus (HurriCANe / OCAN) Standard space-platform service bus with Rx/Tx mailboxes. Pending
P8 SpaceWire (GRSPW2) High-speed DMA-based inter-model connectivity with RMAP support. Pending
P9 RegisterBank refactor Internal refactor: replace bespoke switch-block MMIO with a declarative helper. Background priority. Pending
P10 CPI bucket-resync model Optional cycle-approximate timing layer. Needs human approval before kick-off. Pending

Phase 8 exit criteria

  • Store() → modify guest → Restore() reproduces bit-exact state. (Already met by the Save/Restore implementation; phase 8 keeps it green as new peripherals land.)
  • Cross-model demo: two Emulator instances communicate over SpaceWire RMAP.
  • INTEGRATION.md document describes how to wrap Tero in an SMP2 wrapper.

What is intentionally not in scope

  • Linux as a guest. RTEMS only.
  • Cycle-accurate timing. Tero advances simulated time by a fixed ns_per_insn per instruction. The optional CPI model (P10) trades a configurable accuracy improvement for runtime overhead and is gated on a human go-ahead.
  • Networking peripherals beyond CAN / SpaceWire. GRETH (Ethernet) and libbsd integration are out of scope for the MVP and the planned Phase 8 work.
  • SRMMU and cache control — see the deferral notes in the snapshot above.

Dependency graph

MVP (Phases 0–6)  ✅
    ├── FPU SoftFloat 3e         ✅
    ├── GDB remote stub          ✅
    ├── SMP validation N=2/N=4   ✅
    ├── Save / Restore           ✅
    └── PROM (Boot ROM)          ✅

Performance track (toward 1:1 GR740):
    Phase 10.1 decode cache      ✅
    Phase 10.2 threaded code     ✖ removed (superseded by IR JIT)
    Phase 11 arch-neutral IR     ✅
    Phase 12 tiered LLVM JIT     ✅ (default; LLVM ≥ 18 mandatory)
    Phase 13 multi-thread        ⏳ (standalone-only, ADR-001)

Phase 8 (active, parallel):
    P6 GPIO → P7 Flash → P8 CAN / SpaceWire → P9 RegisterBank
    P10 CPI bucket-resync (parallel, human approval needed)

Deferred:
    P2 Cache control   ⏸ (was a P3 prerequisite only)
    P3 SRMMU           ⏸ (no RTEMS 5 leon3 MMU sub-suite to gate against)

Notes

  • The detailed work plans live under plans/ in the repo root — plans/roadmap.md is the work-tracking source of truth, plans/INDEX.md is the per-plan index, plans/completed/ archives finished work.
  • Tier-A "live status" with test counts and per-area judgement calls is in Status — that document is the chronological log per work session, this one is the steady-state roadmap.
  • For features under construction, file an issue or check plans/ before starting work to avoid duplication.