Glossary¶

Terms used throughout the Tero documentation, grouped by area. If you are new to the LEON/GRLIB/RTEMS ecosystem, read the first two groups before diving into the architecture pages.

Hardware and SoC¶

SPARC V8

The 32-bit RISC instruction set architecture defined by the SPARC International standard. Big-endian, register-window based. Used by Cobham Gaisler's LEON processor family and, historically, by Sun workstations. Tero implements SPARC V8 integer, FPU and privileged instructions.

LEON3 / LEON3FT

Cobham Gaisler's radiation-tolerant (FT = Fault-Tolerant) implementation of the SPARC V8 ISA. LEON3FT adds hardware scrubbing, EDAC registers, and error-injection support. Used in the GR712RC SoC.

LEON4 / LEON4FT

Second-generation Gaisler SPARC core. Higher IPC than LEON3, SPARC V8 compliant. Used in the GR740 SoC.

GR712RC

Cobham Gaisler dual-core LEON3FT SoC (two cores at 80 MHz). The primary Tero target. Contains IRQMP, GPTimer, APBUART, MemCtrl, GRGPIO and more. Used in launchers and scientific satellites.

GR740

Cobham Gaisler quad-core LEON4FT SoC (four cores at 250 MHz). Tero's long-horizon 1:1 real-time target (Phase 9+). Uses IRQAMP instead of IRQMP.

GRLIB

Gaisler's open-source LEON-centric IP-core library. All the built-in peripherals in Tero (IRQMP, GPTimer, APBUART, MemCtrl, GRGPIO …) are GRLIB IP cores with documented register maps.

SPARC register windows

A hardware mechanism where each function call "slides" a window into a deep physical register file (typically 8 windows × 24 user registers). Avoids most push/pop spills for shallow call chains. Controlled by WIM (Window Invalid Mask) and PSR.CWP (current window pointer). Overflowing the window set triggers a window_overflow trap.

Operating system and toolchain¶

RTEMS

Real-Time Executive for Multiprocessor Systems. The standard open-source RTOS for safety-critical embedded and space applications. Tero's primary goal is to run the RTEMS ⅚ testsuite for BSP leon3 at high pass rates.

BSP (Board Support Package)

The hardware-adaptation layer inside RTEMS that initialises the SoC (clocks, memory, console UART, interrupt controller). The leon3 BSP targets both GR712RC and GR740.

RCC (Radiation Compiler Collection)

Cobham Gaisler's SPARC cross-toolchain bundle (based on GCC + newlib). Version RCC 1.3.2 ships RTEMS 5.3 and is the toolchain Tero's build scripts and guest programs are tested against. Default install prefix: /opt/rcc-1.3.2-gcc/.

mkprom2

Cobham Gaisler's PROM image builder. Takes an RTEMS ELF and wraps it in a bootloader-style ROM image (.rom) that can be flashed to PROM or run directly on Tero. The resulting binary self-copies to RAM and jumps to the entry point — matching exactly how real GR712RC silicon boots.

sptests / smptests / fptests

Three RTEMS test suites shipped with the RCC toolchain: sptests — uniprocessor tests; smptests — SMP (multi-core) tests; fptests — floating-point tests. Pass rates against these suites are Tero's primary correctness metric.

SIS

Gaisler's SPARC Instruction Simulator — the closed-source reference simulator shipped with the RCC toolchain. Acts as the oracle for Tero: "Tero passes" means "Tero agrees with SIS on the same test, scored by the same RTEMS algorithm".

CPU registers and state¶

PSR (Processor State Register)

Main SPARC V8 control register. Contains condition codes (N/Z/V/C), the current window pointer (CWP), processor interrupt level (PIL), supervisor bit (S), enable-traps bit (ET), and FPU-enabled (EF).

WIM (Window Invalid Mask)

Bitmask of which register windows are "invalid" (not in use by software). Hardware compares CWP against WIM on SAVE/RESTORE to trigger window-overflow / window-underflow traps.

TBR (Trap Base Register)

Points to the trap table in memory. When a trap fires, the processor computes the handler address as TBR.TBA | (TT << 4), where TT is the trap type byte.

TT (Trap Type)

The numeric code that identifies a trap (e.g. 0x01 = instruction_access_exception, 0x04 = fp_disabled, 0x0b = watchpoint_detected). TT is stored in TBR[7:4] after a trap fires.

ASR19

Ancillary State Register 19 — the LEON power-down register. Writing zero to %asr19 puts the core into low-power idle mode. Tero's idle-time skip fast-forwards simulated time when all cores are blocked on %asr19.

nPC (next Program Counter)

SPARC has both PC (currently executing instruction) and nPC (next instruction). Branch delay slots are implemented by updating nPC before PC advances. RETT (return from trap) restores both.

Emulator concepts¶

SimTimeNs

A strong-typed uint64_t (enum class SimTimeNs : uint64_t) representing nanoseconds of simulated time — not wall-clock time. All scheduling deadlines and peripheral timers are expressed in SimTimeNs.

PhysAddr / VirtAddr / CoreId

Strong-typed wrappers around uint32_t / uint8_t so the compiler rejects accidental mixing. PhysAddr is used for all bus transactions; VirtAddr is reserved for future MMU-aware accessors.

PacingMode

How the emulator relates simulated time to wall-clock time. Realtime (default) — sleep_until between slices so 1 s simulated ≈ 1 s real. Turbo — free-running, no host clock reads; maximum throughput, mandatory for tests and batch tools.

quantum

The number of instructions each core executes before yielding to the next core in the round-robin scheduler. Default 1000. The SMP test harness uses smaller values (200–400) to reduce inter-core handshake latency.

Switch interpreter

Tero's reference execution path — fetch-decode-execute one instruction at a time via a C++ switch over InsnKind. The correctness oracle that the JIT must reproduce bit-for-bit. Selected by EmulatorConfig::translation = false.

JIT (tiered LLVM JIT)

Tero's fast execution path. Translates basic blocks of SPARC instructions to an arch-neutral IR, then lowers to native x86-64 via LLVM ORCv2. Two tiers: Baseline (fast O0 compile) and Optimising (background O2 promotion). Default path (translation = true).

IR (Intermediate Representation)

Tero's arch-neutral IrOp/IrBlock language that sits between the SPARC frontend and the LLVM backend. The IR interpreter serves as a fallback for untranslatable ops and as a correctness oracle for the JIT.

IPeripheral

The C++ interface every device in Tero implements. Methods: mmio_range(), attach(), mmio_read(), mmio_write(), tick(), reset(), publish(), optionally find_port(). Users add custom hardware by implementing this interface.

PeripheralSpec

A data record (instance name + factory + IRQ lines + optional chardev index + optional port connections) that lives in EmulatorConfig::peripherals. The runtime instantiates peripherals from these specs — no global registry or special subclass required.

SMP2 / ECSS concepts¶

SMP2 (ECSS-E-ST-40-07)

The European Cooperation for Space Standardisation simulation modelling standard. Defines a lifecycle (Publish → Configure → Connect → Initialize → Run → Hold → Store → Restore) and service interfaces (ILogger, ITimeKeeper, etc.). Tero's architecture mirrors this lifecycle so it can be wrapped as an SMP2 model without refactoring the core.

SMP2 wrapper

A thin adapter that maps Tero's injected interfaces (ILogger, ITimeSource, ICharacterDevice …) to the corresponding SMP2 environment services. Maintained in a separate repository; not part of the Tero source tree.

GRLIB Plug&Play (PnP)

A self-describing bus topology table embedded in GRLIB SoC designs at a fixed memory address. The RTEMS BSP reads this table at boot to discover peripheral base addresses and IRQ lines. Tero builds a synthetic PnP table matching the configured peripheral map so the BSP finds what it expects.

Peripheral abbreviations¶