GR712RC reference (for users)¶

A user-facing reference for the GR712RC SoC Lince models: the memory map, the peripheral instances and their bases, and the IRQ assignments. The full datasheet map is reproduced below for orientation; the What Lince actually models section shows the subset that gr712rc_config() instantiates today — that is the machine you get when you run --soc gr712rc or call the recipe.

Bases and IRQs here are exactly those wired by gr712rc_config() and declared in soc_family.hpp. For the GR740 quad-core map use --soc gr740 / gr740_config(); for how peripherals are declared and wired generally, see the peripheral reference.

What Lince actually models¶

gr712rc_config() builds these PeripheralSpec entries (in order), plus RAM and PROM. Everything else in the datasheet tables below exists on the silicon but is not instantiated by the recipe (you can add your own via add_peripheral / a custom PeripheralSpec).

Instance	Base	IRQ line(s)	Notes
`irqmp`	`0x80000200`	— (the controller)	Multiprocessor interrupt controller; created first so later specs can allocate IRQ bridges. EIRQ funnel for sources 16–31 (default level 12).
`memctrl`	`0x80000000`	—	FTMCTRL memory controller registers.
`gptimer0`	`0x80000300`	8	General-purpose timer unit (the recipe wires the shared timer IRQ 8). Programs the 1 MHz RTEMS tick.
`apbuart0`	`0x80000100`	2	Console UART → `character_devices[0]`.
`apbuart1`	`0x80100100`	17 (EIRQ)	→ `character_devices[1]`.
`apbuart2`	`0x80100200`	18 (EIRQ)	→ `character_devices[2]`.
`apbuart3`	`0x80100300`	19 (EIRQ)	→ `character_devices[3]`.
`apbuart4`	`0x80100400`	20 (EIRQ)	→ `character_devices[4]`.
`apbuart5`	`0x80100500`	21 (EIRQ)	→ `character_devices[5]`.
`grgpio0`	`0x80000900`	1–15	GPIO port 1 (all 15 APB lines declared; interrupts masked at reset).
`grgpio1`	`0x80000A00`	1–15	GPIO port 2.

SoC-level recipe parameters: num_cores = 2, cpu_clock_hz = 80 MHz, ram_base = 0x40000000, ram_size = 16 MiB (the hello-gr712rc example bumps this to 64 MiB), prom_base = 0x0, prom_size = 32 MiB. Secondary core boots in power-down (released by software via the IRQMP). Use gr712rc_uniprocessor_config() for the same layout with one core.

Datasheet memory map and IRQ assignments¶

Reference tables built strictly from the GR712RC datasheet:

§1.3 / TABLE 1 — Internal memory map
§1.4 / TABLE 2 — Interrupt assignment (mirrored in §8.2.3 / TABLE 40)

Memory regions¶

Region	Address range	Bus	Notes
FTMCTRL — PROM area	`0x00000000 – 0x20000000`	AHB	External PROM via `ROMSN[1:0]`, up to 32 MiB
FTMCTRL — I/O area	`0x20000000 – 0x40000000`	AHB	Memory-mapped I/O via `IOSN`
FTMCTRL — SRAM/SDRAM area	`0x40000000 – 0x80000000`	AHB	External SRAM (`RAMSN[1:0]`) and/or SDRAM (`SDCSN[1:0]`)
APBCTRL-1 (APB bridge)	`0x80000000 – 0x80100000`	AHB	Bridge to APB1
APBCTRL-2 (APB bridge)	`0x80100000 – 0x80200000`	AHB	Bridge to APB2
DSU3	`0x90000000 – 0xA0000000`	AHB	Debug support unit
FTAHBRAM (RAM area)	`0xA0000000 – 0xA0100000`	AHB	On-chip 192 KiB RAM with EDAC
AHB plug&play	`0xFFFFF000 – 0xFFFFFFFF`	AHB	AMBA plug&play

APB1 peripherals (`0x80000000 – 0x80100000`)¶

Core	Address range	IRQ	Function
FTMCTRL	`0x80000000 – 0x80000100`	—	Memory controller registers
APBUART-0	`0x80000100 – 0x80000200`	2	UART0 RX/TX
IRQMP	`0x80000200 – 0x80000300`	12	Multiprocessor interrupt controller (extended IRQ funnel)
GPTIMER	`0x80000300 – 0x80000400`	8-11	4-timer general-purpose timer unit (one IRQ per timer)
SPICTRL	`0x80000400 – 0x80000500`	13	SPI controller (shares IRQ 13 with GRSLINK)
CANMUX	`0x80000500 – 0x80000600`	—	CAN bus multiplexer control
GRGPREG	`0x80000600 – 0x80000700`	—	General-purpose register
GRSCS	`0x80000700 – 0x80000800`	—	Spacecraft clock synchronizer
GRSLINK	`0x80000800 – 0x80000900`	13	SLINK serial (shares IRQ 13 with SPICTRL)
GRGPIO-1	`0x80000900 – 0x80000A00`	1-15	GPIO port 1 (IRQs 3 & 4 are GPIO-only)
GRGPIO-2	`0x80000A00 – 0x80000B00`	1-15	GPIO port 2 (IRQs 3 & 4 are GPIO-only)
GRTM	`0x80000B00 – 0x80000C00`	29-30	Telemetry encoder (29 = data, 30 = time strobe)
I2CMST	`0x80000C00 – 0x80000D00`	28	I²C master
CLKGATE	`0x80000D00 – 0x80000E00`	—	Clock gating unit
GRETH	`0x80000E00 – 0x80000F00`	14	10/100 Ethernet MAC (shares IRQ 14 with B1553BRM, GRTC)
AHBSTAT	`0x80000F00 – 0x80001000`	1	AHB status / EDAC correctable error
APB1 PnP	`0x800FF000 – 0x80100000`	—	APB1 plug&play configuration

APB2 peripherals (`0x80100000 – 0x80200000`)¶

Core	Address range	IRQ	Function
FTAHBRAM (regs)	`0x80100000 – 0x80100100`	—	On-chip RAM configuration register
APBUART-1	`0x80100100 – 0x80100200`	17	UART1 RX/TX
APBUART-2	`0x80100200 – 0x80100300`	18	UART2 RX/TX
APBUART-3	`0x80100300 – 0x80100400`	19	UART3 RX/TX
APBUART-4	`0x80100400 – 0x80100500`	20	UART4 RX/TX
APBUART-5	`0x80100500 – 0x80100600`	21	UART5 RX/TX
GRTIMER	`0x80100600 – 0x80100700`	7	Time-latch general-purpose timer
GRSPW2-0	`0x80100800 – 0x80100900`	22	SpaceWire link 0
GRSPW2-1	`0x80100900 – 0x80100A00`	23	SpaceWire link 1
GRSPW2-2	`0x80100A00 – 0x80100B00`	24	SpaceWire link 2
GRSPW2-3	`0x80100B00 – 0x80100C00`	25	SpaceWire link 3
GRSPW2-4	`0x80100C00 – 0x80100D00`	26	SpaceWire link 4
GRSPW2-5	`0x80100D00 – 0x80100E00`	27	SpaceWire link 5
APB2 PnP	`0x801FF000 – 0x80200000`	—	APB2 plug&play configuration

High AHB peripherals¶

Core	Address range	IRQ	Function
B1553BRM	`0xFFF00000 – 0xFFF01000`	14	MIL-STD-1553B BC/RT/BM (shared IRQ 14)
GRTC	`0xFFF10000 – 0xFFF10100`	14	Telecommand decoder (shared IRQ 14)
Proprietary, do not access	`0xFFF20000 – 0xFFF20100`	—	Reserved
CANOC core 1	`0xFFF30000 – 0xFFF30100`	5	OpenCores CAN core 1
CANOC core 2	`0xFFF30100 – 0xFFF30200`	6	OpenCores CAN core 2

IRQ summary (TABLE 2 / TABLE 40)¶

IRQ	Source(s)	Function
1	AHBSTAT, GRGPIO-½	AHB bus error / EDAC correctable; GPIO IRQs 1-15
2	APBUART-0	UART0 RX/TX
3-4	GRGPIO-½	GPIO-only IRQs
5	CANOC core 1	OCCAN core 1
6	CANOC core 2	OCCAN core 2
7	GRTIMER	Timer underflow
8-11	GPTIMER	One IRQ per timer (4 timers)
12	IRQMP	Extended IRQ funnel for sources 16-31
13	SPICTRL, GRSLINK	Shared SPI / SLINK
14	B1553BRM, GRETH, GRTC	Shared 1553 / Ethernet / Telecommand
15	—	Reserved (non-maskable on LEON3, use with care)
16	ASCS	ASCS interrupt (chained via 12)
17-21	APBUART-1 to APBUART-5	UART RX/TX (chained via 12)
22-27	GRSPW2-0 to GRSPW2-5	SpaceWire RX/TX (chained via 12)
28	I2CMST	I²C master (chained via 12)
29	GRTM	Telemetry encoder data (chained via 12)
30	GRTM	Telemetry encoder time strobe (chained via 12)

Notes: - Interrupts 16-31 reach the CPU as IRQ 12 (extended). Software reads the IRQMP extended-identification register to discover the real source. - IRQ 15 is non-maskable on LEON3 and reserved by most operating systems. - Multiple peripherals on the same IRQ (e.g. 13, 14) require chained handlers.